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In some small-form-factor systems, this may not be sufficient to allow even "half-length" PCI cards to fit. Despite this limitation, these systems are still useful because many modern PCI cards are considerably smaller than half-length.

Each transaction consists of an address phase followed by one or more data phases. The direction of the data phases may be from initiator to target write transaction or vice versa read transaction , but all of the data phases must be in the same direction.

Either party may pause or halt the data phases at any point. One common example is a low-performance PCI device that does not support burst transactions , and always halts a transaction after the first data phase.

Any PCI device may initiate a transaction. First, it must request permission from a PCI bus arbiter on the motherboard.

The arbiter grants permission to one of the requesting devices. The initiator begins the address phase by broadcasting a bit address plus a 4-bit command code, then waits for a target to respond.

All other devices examine this address and one of them responds a few cycles later. The initiator broadcasts the low 32 address bits, accompanied by a special "dual address cycle" command code.

Devices which do not support bit addressing can simply not respond to that command code. The next cycle, the initiator transmits the high 32 address bits, plus the real command code.

The transaction operates identically from that point on. To ensure compatibility with bit PCI devices, it is forbidden to use a dual address cycle if not necessary, i.

While the PCI bus transfers 32 bits per data phase, the initiator transmits 4 active-low byte enable signals indicating which 8-bit bytes are to be considered significant.

In particular, a write must affect only the enabled bytes in the target PCI device. The PCI standard explicitly allows a data phase with no bytes enabled, which must behave as a no-op.

Each PCI slot gets its own configuration space address range. When a computer is first turned on, all PCI devices respond only to their configuration space accesses.

If an address is not claimed by any device, the transaction initiator's address phase will time out causing the initiator to abort the operation.

PCI devices therefore generally attempt to avoid using the all-ones value in important status registers, so that such an error can be easily detected by software.

There are 16 possible 4-bit command codes, and 12 of them are assigned. With the exception of the unique dual address cycle, the least significant bit of the command code indicates whether the following data phases are a read data sent from target to initiator or a write data sent from an initiator to target.

PCI targets must examine the command code as well as the address and not respond to address phases which specify an unsupported command code.

The commands that refer to cache lines depend on the PCI configuration space cache line size register being set up properly; they may not be used until that has been done.

Soon after promulgation of the PCI specification, it was discovered that lengthy transactions by some devices, due to slow acknowledgments, long data bursts, or some combination, could cause buffer underrun or overrun in other devices.

Recommendations on the timing of individual phases in Revision 2. Additionally, as of revision 2. If the timer has expired and the arbiter has removed GNT , then the initiator must terminate the transaction at the next legal opportunity.

This is usually the next data phase, but Memory Write and Invalidate transactions must continue to the end of the cache line. Devices unable to meet those timing restrictions must use a combination of posted writes for memory writes and delayed transactions for other writes and all reads.

In a delayed transaction, the target records the transaction including the write data internally and aborts asserts STOP rather than TRDY the first data phase.

The initiator must retry exactly the same transaction later. In the interim, the target internally performs the transaction, and waits for the retried transaction.

When the retried transaction is seen, the buffered result is delivered. A device may be the target of other transactions while completing one delayed transaction; it must remember the transaction type, address, byte selects and if a write data value, and only complete the correct transaction.

If the target has a limit on the number of delayed transactions that it can record internally simple targets may impose a limit of 1 , it will force those transactions to retry without recording them.

They will be dealt with when the current delayed transaction is completed. If two initiators attempt the same transaction, a delayed transaction begun by one may have its result delivered to the other; this is harmless.

The latter should never happen in normal operation, but it prevents a deadlock of the whole bus if one initiator is reset or malfunctions.

The PCI standard permits multiple independent PCI buses to be connected by bus bridges that will forward operations on one bus to another when required.

Although conventional PCI tends not to use many bus bridges, PCI express systems use many; each PCI express slot appears to be a separate bus, connected by a bridge to the others.

Generally, when a bus bridge sees a transaction on one bus that must be forwarded to the other, the original transaction must wait until the forwarded transaction completes before a result is ready.

One notable exception occurs in the case of memory writes. Here, the bridge may record the write data internally if it has room and signal completion of the write before the forwarded write has completed.

Or, indeed, before it has begun. Such "sent but not yet arrived" writes are referred to as "posted writes", by analogy with a postal mail message.

Although they offer great opportunity for performance gains, the rules governing what is permissible are somewhat intricate.

The PCI standard permits bus bridges to convert multiple bus transactions into one larger transaction under certain situations.

This can improve the efficiency of the PCI bus. There are two additional arbitration signals REQ and GNT which are used to obtain permission to initiate a transaction.

All are active-low , meaning that the active or asserted state is a low voltage. Pull-up resistors on the motherboard ensure they will remain high inactive or deasserted if not driven by any device, but the PCI bus does not depend on the resistors to change the signal level; all devices drive the signals high for one cycle before ceasing to drive the signals.

All PCI bus signals are sampled on the rising edge of the clock. Signals nominally change on the falling edge of the clock, giving each PCI device approximately one half a clock cycle to decide how to respond to the signals it observed on the rising edge, and one half a clock cycle to transmit its response to the other device.

The PCI bus requires that every time the device driving a PCI bus signal changes, one turnaround cycle must elapse between the time the one device stops driving the signal and the other device starts.

Without this, there might be a period when both devices were driving the signal, which would interfere with bus operation. The combination of this turnaround cycle and the requirement to drive a control line high for one cycle before ceasing to drive it means that each of the main control lines must be high for a minimum of two cycles when changing owners.

The PCI bus protocol is designed so this is rarely a limitation; only in a few special cases notably fast back-to-back transactions is it necessary to insert additional delay to meet this requirement.

Any device on a PCI bus that is capable of acting as a bus master may initiate a transaction with any other device.

To ensure that only one transaction is initiated at a time, each master must first wait for a bus grant signal, GNT , from an arbiter located on the motherboard.

Each device has a separate request line REQ that requests the bus, but the arbiter may "park" the bus grant signal at any device if there are no current requests.

The arbiter may remove GNT at any time. The arbiter may also provide GNT at any time, including during another master's transaction.

A device may initiate a transaction at any time that GNT is asserted and the bus is idle. A PCI bus transaction begins with an address phase. Actually, the time to respond is 2.

Note that a device must latch the address on the first cycle; the initiator is required to remove the address and command from the bus on the following cycle, even before receiving a DEVSEL response.

The additional time is available only for interpreting the address and command after it is captured. On the fifth cycle of the address phase or earlier if all other devices have medium DEVSEL or faster , a catch-all "subtractive decoding" is allowed for some address ranges.

On the sixth cycle, if there has been no response, the initiator may abort the transaction by deasserting FRAME.

PCI devices therefore are generally designed to avoid using the all-ones value in important status registers, so that such an error can be easily detected by software.

Targets latch the address and begin decoding it. Subtractive decode devices, seeing no other response by clock 4, may respond on clock 5. If the master does not see a response by clock 5, it will terminate the transaction and remove FRAME on clock 6.

The initiator may assert IRDY as soon as it is ready to transfer data, which could theoretically be as soon as clock 2. To allow bit addressing, a master will present the address over two consecutive cycles.

On the following cycle, it sends the high-order address bits and the actual command. Dual-address cycles are forbidden if the high-order address bits are zero, so devices which do not support bit addressing can simply not respond to dual cycle commands.

Addresses for PCI configuration space access are decoded specially. For these, the low-order address lines specify the offset of the desired PCI configuration register, and the high-order address lines are ignored.

Each slot connects a different high-order address line to the IDSEL pin, and is selected using one-hot encoding on the upper address lines.

After the address phase specifically, beginning with the cycle that DEVSEL goes low comes a burst of one or more data phases. In case of a write, the asserted signals indicate which of the four bytes on the AD bus are to be written to the addressed location.

In the case of a read, they indicate which bytes the initiator is interested in. For reads, it is always legal to ignore the byte enable signals and simply return all 32 bits; cacheable memory resources are required to always return 32 valid bits.

The data phase continues until both parties are ready to complete the transfer and continue to the next data phase.

Whichever side is providing the data must drive it on the AD bus before asserting its ready signal. Once one of the participants asserts its ready signal, it may not become un-ready or otherwise alter its control signals until the end of the data phase.

The data recipient must latch the AD bus each cycle until it sees both IRDY and TRDY asserted, which marks the end of the current data phase and indicates that the just-latched data is the word to be transferred.

This continues the address cycle illustrated above, assuming a single address cycle with medium DEVSEL, so the target responds in time for clock 3.

However, at that time, neither side is ready to transfer data. For clock 4, the initiator is ready, but the target is not. On clock 5, both are ready, and a data transfer takes place as indicated by the vertical lines.

For clock 6, the target is ready to transfer, but the initiator is not. On clock 7, the initiator becomes ready, and data is transferred.

For clocks 8 and 9, both sides remain ready to transfer data, and data is transferred at the maximum possible rate 32 bits per clock cycle.

In case of a read, clock 2 is reserved for turning around the AD bus, so the target is not permitted to drive data on the bus even if it is capable of fast DEVSEL.

A target that supports fast DEVSEL could in theory begin responding to a read the cycle after the address is presented. This cycle is, however, reserved for AD bus turnaround.

Note that most targets will not be this fast and will not need any special logic to enforce this condition. Either side may request that a burst end after the current data phase.

Simple PCI devices that do not support multi-word bursts will always request this immediately. Even devices that do support bursts will have some limit on the maximum length they can support, such as the end of their addressable memory.

The cycle after the target asserts TRDY , the final data transfer is complete, both sides deassert their respective RDY signals, and the bus is idle again.

Obviously, it is pointless to wait for TRDY in such a case. The target requests the initiator end a burst by asserting STOP.

The initiator will then end the transaction by deasserting FRAME at the next legal opportunity; if it wishes to transfer more data, it will continue in a separate transaction.

There are several ways for the target to do this:. There will always be at least one more cycle after a target-initiated disconnection, to allow the master to deassert FRAME.

There are two sub-cases, which take the same amount of time, but one requires an additional data phase:. If the initiator ends the burst at the same time as the target requests disconnection, there is no additional bus cycle.

For memory space accesses, the words in a burst may be accessed in several orders. The unnecessary low-order address bits AD[1: A target which does not support a particular order must terminate the burst after the first word.

Some of these orders depend on the cache line size, which is configurable on all PCI devices. If the starting offset within the cache line is zero, all of these modes reduce to the same order.

Cache line toggle and cache line wrap modes are two forms of critical-word-first cache line fetching.

Toggle mode XORs the supplied address with an incrementing counter. This is the native order for Intel and Pentium processors.

It has the advantage that it is not necessary to know the cache line size to implement it. When one cache line is completely fetched, fetching jumps to the starting offset in the next cache line.

Note that most PCI devices only support a limited range of typical cache line sizes; if the cache line size is programmed to an unexpected value, they force single-word access.

This is rarely used, and may be buggy in some devices; they may not support it, but not properly force single-word access either.

That might be their turnaround cycle. As the initiator is also ready, a data transfer occurs. This repeats for three more cycles, but before the last one clock edge 5 , the master deasserts FRAME , indicating that this is the end.

On clock edge 7, another initiator can start a different transaction. This is also the turnaround cycle for the other control lines.

The equivalent read burst takes one more cycle, because the target must wait 1 cycle for the AD bus to turn around before it may assert TRDY:.

On clock edge 6, the target indicates that it wants to stop with data , but the initiator is already holding IRDY low, so there is a fifth data phase clock edge 7 , during which no data is transferred.

The PCI bus detects parity errors, but does not attempt to correct them by retrying operations; it is purely a failure indication.

Due to this, there is no need to detect the parity error before it has happened, and the PCI bus actually detects it a few cycles later.

During a data phase, whichever device is driving the AD[

These are typically necessary for devices used during system startup, before device drivers are loaded by the operating system. Note, this does not apply to PCI Express.

How this works is that each PCI device that can operate in bus-master mode is required to implement a timer, called the Latency Timer, that limits the time that device can hold the PCI bus.

The timer starts when the device gains bus ownership, and counts down at the rate of the PCI clock. When the counter reaches zero, the device is required to release the bus.

If no other devices are waiting for bus ownership, it may simply grab the bus again and transfer more data. Devices are required to follow a protocol so that the interrupt lines can be shared.

The PCI bus includes four interrupt lines, all of which are available to each device. However, they are not wired in parallel as are the other PCI bus lines.

Single-function devices use their INTA for interrupt signaling, so the device load is spread fairly evenly across the four available interrupt lines.

This alleviates a common problem with sharing interrupts. The mapping of PCI interrupt lines onto system interrupt lines, through the PCI host bridge, is implementation-dependent.

Platform-specific BIOS code is meant to know this, and set the "interrupt line" field in each device's configuration space indicating which IRQ it is connected to.

PCI interrupt lines are level-triggered. This was chosen over edge-triggering in order to gain an advantage when servicing a shared interrupt line, and for robustness: Later revisions of the PCI specification add support for message-signaled interrupts.

In this system, a device signals its need for service by performing a memory write, rather than by asserting a dedicated line. This alleviates the problem of scarcity of interrupt lines.

Even if interrupt vectors are still shared, it does not suffer the sharing problems of level-triggered interrupts.

It also resolves the routing problem, because the memory write is not unpredictably modified between device and host. Finally, because the message signaling is in-band , it resolves some synchronization problems that can occur with posted writes and out-of-band interrupt lines.

PCI Express does not have physical interrupt lines at all. It uses message-signaled interrupts exclusively. The PCI specification also provides options for 3.

Any number of bus masters can reside on the PCI bus, as well as requests for the bus. One pair of request and grant signals is dedicated to each bus master.

Typical PCI cards have either one or two key notches, depending on their signaling voltage. This allows cards to be fitted only into slots with a voltage they support.

The PCI connector is defined as having 62 contacts on each side of the edge connector , but two or four of them are replaced by key notches, so a card has 60 or 58 contacts on each side.

Side A refers to the 'solder side' and side B refers to the 'component side': The pinout of B and A sides are as follows, looking down into the motherboard connector pins A1 and B1 are closest to backplate.

Most bit PCI cards will function properly in bit PCI-X slots, but the bus clock rate will be limited to the clock frequency of the slowest card, an inherent limitation of PCI's shared bus topology.

For example, when a PCI 2. Many bit PCI-X cards are designed to work in bit mode if inserted in shorter bit connectors, with some loss of performance.

Installing a bit PCI-X card in a bit slot will leave the bit portion of the card edge connector not connected and overhanging. This requires that there be no motherboard components positioned so as to mechanically obstruct the overhanging portion of the card edge connector.

The maximum width of a PCI card is Two bracket heights have been specified, known as full-height and low-profile. The bracket or backplate is the part that fastens to the card cage to stabilize the card.

It also usually contains external connectors, so it attaches in a window in the computer case so any connectors are accessible from outside.

The backplate is typically fixed to the case by either a or M3 screw , or with a separate hold-down bracket that is part of the case.

For each bracket height two different lengths have been specified for a total of four lengths, known as full-length and half-length for full-height cards, and MD1 and MD2 for low-profile cards.

The height includes the card edge connector. However, most modern PCI cards are half-length or smaller see below and many modern PC cases cannot accommodate the length of a full-size card.

Note, this length is the length of the printed circuit board; it does not include the angled short leg of the metal bracket which does affect e.

Some high power PCI products have active cooling systems that extend past the nominal dimensions.

Likewise, some may take up more than one slot space: A half-length full-height card has a length of up to The actual dimensions of many cards described as half-length full-height are lower than these maximums and they will still fit any standard full-height PCI slot as long as they use a properly located full-height bracket.

The low-profile specification assumes a 3. The retention screw has also been moved 1. The low profile card itself has a maximum height of The smaller bracket will not fit a standard desktop, tower or 3U rack-mount PC case, but will fit in many newer small form-factor SFF desktop cases or in a 2U rack-mount case.

These cards may be known by other names such as "slim". Many manufacturers supply both types of bracket with cards, where the bracket is typically attached to the card with a pair of screws allowing the installer to easily change it.

MD1 defines the shortest bit PCI card length, MD2 defines the maximum length of a low profile PCI card as This is the most common low-profile card form-factor.

The standard size for Mini PCI cards is approximately a quarter of their full-sized counterparts.

There is no access to the card from outside the case, unlike desktop PCI cards with brackets carrying connectors. This limits the kinds of functions a Mini PCI card can perform.

There are three card form factors: The card connector used for each type include: These cards must be located at the edge of the computer or docking station so that the RJ11 and RJ45 ports can be mounted for external access.

In some small-form-factor systems, this may not be sufficient to allow even "half-length" PCI cards to fit. Despite this limitation, these systems are still useful because many modern PCI cards are considerably smaller than half-length.

Each transaction consists of an address phase followed by one or more data phases. The direction of the data phases may be from initiator to target write transaction or vice versa read transaction , but all of the data phases must be in the same direction.

Either party may pause or halt the data phases at any point. One common example is a low-performance PCI device that does not support burst transactions , and always halts a transaction after the first data phase.

Any PCI device may initiate a transaction. First, it must request permission from a PCI bus arbiter on the motherboard.

The arbiter grants permission to one of the requesting devices. The initiator begins the address phase by broadcasting a bit address plus a 4-bit command code, then waits for a target to respond.

All other devices examine this address and one of them responds a few cycles later. The initiator broadcasts the low 32 address bits, accompanied by a special "dual address cycle" command code.

Devices which do not support bit addressing can simply not respond to that command code. The next cycle, the initiator transmits the high 32 address bits, plus the real command code.

The transaction operates identically from that point on. To ensure compatibility with bit PCI devices, it is forbidden to use a dual address cycle if not necessary, i.

While the PCI bus transfers 32 bits per data phase, the initiator transmits 4 active-low byte enable signals indicating which 8-bit bytes are to be considered significant.

In particular, a write must affect only the enabled bytes in the target PCI device. The PCI standard explicitly allows a data phase with no bytes enabled, which must behave as a no-op.

Each PCI slot gets its own configuration space address range. When a computer is first turned on, all PCI devices respond only to their configuration space accesses.

If an address is not claimed by any device, the transaction initiator's address phase will time out causing the initiator to abort the operation.

PCI devices therefore generally attempt to avoid using the all-ones value in important status registers, so that such an error can be easily detected by software.

There are 16 possible 4-bit command codes, and 12 of them are assigned. With the exception of the unique dual address cycle, the least significant bit of the command code indicates whether the following data phases are a read data sent from target to initiator or a write data sent from an initiator to target.

PCI targets must examine the command code as well as the address and not respond to address phases which specify an unsupported command code.

The commands that refer to cache lines depend on the PCI configuration space cache line size register being set up properly; they may not be used until that has been done.

Soon after promulgation of the PCI specification, it was discovered that lengthy transactions by some devices, due to slow acknowledgments, long data bursts, or some combination, could cause buffer underrun or overrun in other devices.

Recommendations on the timing of individual phases in Revision 2. Additionally, as of revision 2. If the timer has expired and the arbiter has removed GNT , then the initiator must terminate the transaction at the next legal opportunity.

This is usually the next data phase, but Memory Write and Invalidate transactions must continue to the end of the cache line. Devices unable to meet those timing restrictions must use a combination of posted writes for memory writes and delayed transactions for other writes and all reads.

In a delayed transaction, the target records the transaction including the write data internally and aborts asserts STOP rather than TRDY the first data phase.

The initiator must retry exactly the same transaction later. In the interim, the target internally performs the transaction, and waits for the retried transaction.

When the retried transaction is seen, the buffered result is delivered. A device may be the target of other transactions while completing one delayed transaction; it must remember the transaction type, address, byte selects and if a write data value, and only complete the correct transaction.

If the target has a limit on the number of delayed transactions that it can record internally simple targets may impose a limit of 1 , it will force those transactions to retry without recording them.

They will be dealt with when the current delayed transaction is completed. If two initiators attempt the same transaction, a delayed transaction begun by one may have its result delivered to the other; this is harmless.

The latter should never happen in normal operation, but it prevents a deadlock of the whole bus if one initiator is reset or malfunctions.

The PCI standard permits multiple independent PCI buses to be connected by bus bridges that will forward operations on one bus to another when required.

Although conventional PCI tends not to use many bus bridges, PCI express systems use many; each PCI express slot appears to be a separate bus, connected by a bridge to the others.

Generally, when a bus bridge sees a transaction on one bus that must be forwarded to the other, the original transaction must wait until the forwarded transaction completes before a result is ready.

One notable exception occurs in the case of memory writes. Here, the bridge may record the write data internally if it has room and signal completion of the write before the forwarded write has completed.

Or, indeed, before it has begun. Such "sent but not yet arrived" writes are referred to as "posted writes", by analogy with a postal mail message.

Although they offer great opportunity for performance gains, the rules governing what is permissible are somewhat intricate.

The PCI standard permits bus bridges to convert multiple bus transactions into one larger transaction under certain situations.

This can improve the efficiency of the PCI bus. There are two additional arbitration signals REQ and GNT which are used to obtain permission to initiate a transaction.

All are active-low , meaning that the active or asserted state is a low voltage. Pull-up resistors on the motherboard ensure they will remain high inactive or deasserted if not driven by any device, but the PCI bus does not depend on the resistors to change the signal level; all devices drive the signals high for one cycle before ceasing to drive the signals.

All PCI bus signals are sampled on the rising edge of the clock. Signals nominally change on the falling edge of the clock, giving each PCI device approximately one half a clock cycle to decide how to respond to the signals it observed on the rising edge, and one half a clock cycle to transmit its response to the other device.

The PCI bus requires that every time the device driving a PCI bus signal changes, one turnaround cycle must elapse between the time the one device stops driving the signal and the other device starts.

Without this, there might be a period when both devices were driving the signal, which would interfere with bus operation. The combination of this turnaround cycle and the requirement to drive a control line high for one cycle before ceasing to drive it means that each of the main control lines must be high for a minimum of two cycles when changing owners.

The PCI bus protocol is designed so this is rarely a limitation; only in a few special cases notably fast back-to-back transactions is it necessary to insert additional delay to meet this requirement.

Any device on a PCI bus that is capable of acting as a bus master may initiate a transaction with any other device. To ensure that only one transaction is initiated at a time, each master must first wait for a bus grant signal, GNT , from an arbiter located on the motherboard.

Each device has a separate request line REQ that requests the bus, but the arbiter may "park" the bus grant signal at any device if there are no current requests.

The arbiter may remove GNT at any time. The arbiter may also provide GNT at any time, including during another master's transaction. A device may initiate a transaction at any time that GNT is asserted and the bus is idle.

A PCI bus transaction begins with an address phase. Actually, the time to respond is 2. Note that a device must latch the address on the first cycle; the initiator is required to remove the address and command from the bus on the following cycle, even before receiving a DEVSEL response.

The additional time is available only for interpreting the address and command after it is captured. On the fifth cycle of the address phase or earlier if all other devices have medium DEVSEL or faster , a catch-all "subtractive decoding" is allowed for some address ranges.

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